The present invention relates to a semiconductor device including a Group III–V nitride semiconductor, and in particular relates to a field effect semiconductor device in which an electrode is provided on a bottom surface of a substrate.
Group III–V nitride semiconductors such as gallium nitride (GaN), aluminum nitride (AlN) and indium nitride, i.e., a mixed crystal thereof represented by the following general formula: AlxGa1-x-yInyN (where 0≦x≦1, and 0≦y≦1), are examined not only for application to a short-wavelength optical device that utilizes a wide bandgap and a direct transition type band structure, which are physical properties of the mixed crystal, but also for application to an electron device because of the other properties of the mixed crystal such as a high breakdown electric field and a high saturation electron velocity.
In particular, a heterojunction field effect transistor (hereinafter, will be called an “HFET”) that utilizes a two-dimensional electron gas (hereinafter, will be called “2DEG”) generated at the interface between an AlxGa1-xN layer (where 0<x≦1) and a GaN layer, sequentially epitaxially grown over a semi-insulating substrate, is being developed as a high-power device or a high-frequency device. This HFET is characterized, for example, by allowing not only supply of electrons from a carrier supply layer (i.e., an N-type AlGaN barrier layer) but also supply of electrical charges due to polarization effects including spontaneous polarization and piezo-polarization, and by having an electron density higher than 1013 cm−2 which is approximately ten times as large as that of an AlGaAs/GaAs-containing FET. Therefore, this HFET can be expected to have a drain current density higher than that of a GaAs-based HFET, and a device with a maximum drain current exceeding 1 A/mm is reported (see, for example, “Characterization of High Breakdown Voltage AlGaN/GaN Heterojunction FETs with a Field Plate Gate” written by Yuji Ando, Yasuhiro Okamoto, Hironobu Miyamoto, Tatsumine Nakayama, Takashi Inoue and Masaaki Kuzuhara, Technical Report of IEICE, ED2002-214, CPM2002-105(2002-10), pp. 29–34). Further, since a Group III–V nitride semiconductor (such as GaN) has a wide bandgap (of 3.4 eV, for example), the resulting device exhibits a high breakdown voltage characteristic, and thus a breakdown voltage between gate and drain electrodes can be equal to or higher than 100V (see the aforementioned document). As described above, since an electron device including a Group III–V nitride semiconductor, typified by an HFET, can be expected to exhibit electrical characteristics that achieve high breakdown voltage and high current density, such an electron device is examined for application as a high-frequency device or as a device that can deal with high power with a design size smaller than a conventional one.
However, although an electron device including a Group III–V nitride semiconductor is promising as a high-frequency or high-power device, various contrivances have to be made for implementation of such an electron device. As a contrivance for implementing the device that exhibits high-frequency characteristic and high-power characteristic, a technique for using a via hole structure is known.
Hereinafter, a FET that uses such a conventional via hole structure will be described with reference to FIG. 14.
As shown in FIG. 14, a semiconductor layer 102 made of N-type GaAs and including a channel layer (active layer) is formed on an insulative substrate 101 made of gallium arsenide (GaAs) whose thickness is reduced to about 25 μm. Formed on the semiconductor layer 102 are: a Schottky electrode 103; and ohmic source electrode 104 and drain electrode 105 which are provided on both sides of the Schottky electrode 103. A via hole 106 is selectively formed in portions of the insulative substrate 101 and the semiconductor layer 102 which are located below the source electrode 104. On a surface of the insulative substrate 101 opposite to the semiconductor layer 102 (i.e., a bottom surface of the insulative substrate 101), a bottom-surface electrode 107 is formed so as to fill the via hole 106, and the bottom-surface electrode 107 is connected to a ground power supply 108. It is reported that since the FET, whose source electrode 104 is grounded via the bottom-surface electrode 107 and the via hole 106 in this manner, can reduce its source inductance as compared with a FET whose source electrode 104 is grounded via wiring, the former FET achieves an improvement in linear gain by about 2 dB (see, for example, “Basis for GaAs Field Effect Transistor” written by Masumi Fukuda and Yasutaka Hirachi, The Institute of Electronics, Information and Communication Engineers, 1992, p.214).
In addition, as one of other conventional examples, Japanese Unexamined Patent Publication No. 2002-536847 discloses a structure in which a source electrode or emitter electrode is connected to a conductive P+-type substrate grounded through a via hole; on the other hand, Japanese Unexamined Patent Publication No. 11-45892 discloses a structure and a fabrication method in which a substrate made of silicon carbide (SiC) or sapphire is polished to reduce the thickness thereof, and a via hole is formed from the bottom surface of the polished substrate by etching.
Besides, Japanese Unexamined Patent Publication No. 05-21474 discloses a structure in which side faces of a through-type via hole and the bottom surface of a substrate are covered with an insulating film.
However, the structure that uses the aforementioned conventional via hole presents the following problems.
First, due to an electric field applied between the substrate 101 and the semiconductor layer 102 including the active layer, a leakage current is produced between the substrate 101 and the semiconductor layer 102. Secondly, SiC or sapphire used for the substrate 101 is normally very hard and highly resistant to chemicals; therefore, it is considerably difficult to form the via hole 106 in the substrate 101 made of SiC or sapphire so that the via hole 106 passes therethrough to reach the bottom surface of the substrate 101, while maintaining the strength of the substrate 101, i.e., while not reducing the thickness of the substrate 101. On the other hand, if the substrate 101 made of SiC or sapphire is polished to reduce its thickness and then the via hole 106 is formed, the substrate 101 whose thickness is reduced becomes fragile, and therefore, the situation where the substrate 101 is cracked in the step of forming the via hole 106 is brought about.
Accordingly, the semiconductor device connected to the bottom-surface electrode 107 through the conventional via hole presents the problem that the device cannot sufficiently achieve high-frequency characteristic and high-power characteristic.